1. Field of the Invention
The present invention relates to semiconductor devices and in particular, a decrease in negative influences on the semiconductor device's performance due to dispersion of impurity density in a process for the manufacture of the semiconductor devices.
The present application claims priority on Japanese Patent Application No. 2008-293349, the content of which is incorporated herein by reference.
2. Description of Related Art
Dynamic random-access memories (DRAM) are constituted of memory cells, each of which is configured of a single capacitor for accumulating data and a single switching transistor for reading and writing data with the capacitor.
Progressing highly integrated structures of memories reduces the amount of charges accumulated in capacitors so as to reduce magnitudes of signals read from capacitors by switching transistors; hence, they require sense amplifiers to amplify signals having small voltages. This technology has been developed and disclosed in various documents such as Patent Document 1.    Patent Document 1: Japanese Unexamined Patent Application Publication No. 2000-77628
FIG. 5 shows an example of a sense amplifier circuit including a pair of sense amplifiers located between adjacent memory cells included in a sub-cell array.
Specifically, a sense amplifier (which is coupled with a memory cell located in the left side of FIG. 5) is constituted of a pair of n-channel MOS transistors (hereinafter, referred to as NMOS transistors) 2-N4a and 2-N5a and a pair of p-channel MOS transistors (hereinafter, referred to as PMOS transistors) 2-P1a and 2-P2a. 
In connection with the above sense amplifier, an NMOS transistor 2-N1a is used to equalize bit lines BLTa and BLBa to the same potential, while NMOS transistors 2-N6a and 2-N7a are used to precharge the bit lines BLTa and BLBa.
Another sense amplifier (which is coupled with another memory cell located in the right side of FIG. 5) is constituted of NMOS transistors 2-N4b and 2-N5b and PMOS transistors 2-P1b and 2-P2b. 
In connection with the above sense amplifier, an NMOS transistor 2-N1b is used to equalize bit lines BLTb and BLBb to the same potential, while NMOS transistors 2-N6b and 2-N7b are used to precharge the bit lines BLTb and BLBb.
Next, the operation of the sense amplifier circuit of FIG. 5 will be described with reference to FIGS. 6A to 6E, which show a read operation for reading data “1” from the memory cell coupled with the bit line BLTa.
A precharge voltage VBL (e.g. 0.6 V) is applied to a signal line LVBL while a BL-equalize-MOS-activate signal having a high level (corresponding to an internal drive voltage VDD, e.g. 1.4 V) is applied to the gates of the NMOS transistors 2-N1a, 2-N6a, and 2-N7a via a signal line BLEQT. In this state, the NMOS transistors 2-N1a, 2-N6a, and 2-N7a are turned on so as to equalize the bit lines BLTa and BLBa to the precharge voltage VBL. At this time, the drive voltage is stopped to be supplied to nodes SA-N-MOS and SA-P-MOS, which are thus equalized with the precharge voltage VBL.
When the BL-equalize-MOS-activate signal applied to the signal line BLEQT is turned to a low level (corresponding to a ground potential VSS, e.g. 0 V), the NMOS transistors 2-N1a, 2-N6a, and 2-N7a are turned off, thus resetting the bit lines BLTa and BLBa to an open state.
When a word line WL coupled with the memory cell is activated at a high level (corresponding to VPP, e.g. 2.7 V), a charge accumulated in a capacitor of the memory cell is transferred onto the bit line BLTa, thus increasing the potential of the bit line BLTa by ΔV in response to charge transfer.
Since the potential of the bit line BLBa is maintained at the precharge voltage VBL, a potential difference ΔV occurs between the bit lines BLTa and BLBa.
Due to a drive voltage applied to the sense amplifier circuit, the node SA-N-MOS is set to the ground potential VSS while the node SA-P-MOS is set to VDL (e.g. 1.2 V). Compared to the PMOS transistor 2-P2a whose gate is connected to the bit line BLTa, the PMOS transistor 2-P1a whose gate is connected to the bit line BLBa is firstly turned on with a small on-resistance due to a decrease of the potential difference ΔV.
Compared to the NMOS transistor 2-N4a whose gate is connected to the bit line BLBa, the NMOS transistor 2-N5a whose gate is connected to the bit line BLTa is firstly turned on with a small on-resistance due to an increase of the potential difference ΔV.
This increases the potential of the bit line BLTa while decreasing the potential of the bit line BLBa, so that the potential of the bit line BLTa will reach VDL while the potential of the bit line BLBa will reach VSS, thus completing the operation of the sense amplifier.
Thereafter, a column-select signal is set to a high level so that the potential of the bit line BLTa is transferred onto a local IO line LIOTa while the potential of the bit line BLBa is transferred onto a local IO line LIOBa.
This completes the read operation for reading data from the memory cell. In order to subsequently read data from the memory cell, the BL-equalize-MOS-activate signal having a high level is supplied to the gates of the NMOS transistors 2-N1a, 2-N6a, and 2-N7a via the signal line BLEQT, thus equalizing the bit lines BLTa and BLBa with the precharge voltage VBL. This makes it possible to subsequently read data from the memory cell.
The present inventors have recognized the following drawbacks and their causes with respect to the sense amplifier circuit of FIG. 5.
Since the sense amplifier constituted of the PMOS transistors 2-P1a and 2-P2a and the NMOS transistors 2-N4a and 2-N5a amplifies the potential difference ΔV between the hit lines BLTa and BLBa in the read operation for reading data from the memory cell, a difference of threshold voltage Vth between the PMOS transistors 2-P1a and 2-P2a and a difference of threshold voltage Vth between the NMOS transistors 2-N4a and 2-N5a should be substantially smaller than the potential difference ΔV.
When the difference of the threshold voltage Vth between the paired PMOS transistors and the difference of threshold voltage Vth between the paired NMOS transistors are larger than the potential difference ΔV, the sense amplifier cannot perform amplification based on the potential difference ΔV so as to fail to read data from the memory cell.
For this reason, the sense amplifier circuit of FIG. 5 must be designed to precisely set the threshold voltages Vth of the MOS transistors forming the sense amplifiers.
FIG. 7 shows a layout of the sense amplifier circuit of FIG. 5, wherein an n-type well NW1 is sandwiched between p-type wells PW1 and PW2 and wherein the PMOS transistors 2-P1a, 2-P1b, 2-P2a, and 2-P2b forming the sense amplifiers are formed in the n-type well NW1.
For the sake of convenience, FIG. 7 does not include illustrations of elements other than the N-type well NW1, the P-type wells PW1 and PW2 as well as gate wiring layers and diffusion layers forming sources and drains of transistors.
In the actuality, numerous sense amplifier circuits (each shown in FIG. 7) are linearly aligned (Y-direction in FIG. 7) such that both ends of the sense amplifier circuits serve as dummy sense amplifier circuits.
In the fabrication of the wells in FIG. 7, ions of p-type impurities are implanted into a semiconductor substrate (not shown) so as to form a p-type well PW, and then ions of n-type impurities are implanted into the semiconductor substrate so as to form the n-type well NW1 thus dividing the p-type well PW into the p-type wells PW1 and PW2. In this process shown in FIG. 8, a photoresist is formed on the entire surface of a wafer and is then removed from the prescribed region used for the formation of the n-type well NW1; thereafter, n-type impurities are doped into the prescribed region.
The NMOS transistors of the sense amplifier circuit are formed in the p-type wells PW1 and PW2, while the PMOS transistors are formed in the n-type well NW1.
The present inventors checked the operation of the sense amplifier circuit (which is actually produced with the constitution shown in FIGS. 5 and 7) so as to discover that the read operation may not be always performed with the expected performance. To solve such a drawback, the present inventors analyzed device characteristics so as to find out dispersions regarding the threshold voltages Vth of the transistors forming the sense amplifiers, in particularly, relatively large dispersions regarding the threshold voltages Vth of the PMOS transistor 2-P1a and 2-P1b. 
The inventors further analyzed the causes of dispersions of threshold voltages Vth so as to assert that the PMOS transistors 2-P1a and 2-P2a (forming the sense amplifier) and the PMOS transistors 2-P1b and 2-P2b (forming another sense amplifier) are linearly aligned in the n-type well NW1.
In the linear alignment, n-type impurities used for the formation of the n-type well NW1 are implanted for the side wall of the photoresist with a certain angle; hence, they may be reflected at the side wall or its proximate portion of the photoresist, or they may not properly implanted into the prescribed region so as to form ion-implantation-incomplete regions A1 and A2 lying around an ion-implantation-complete region B due to the shade of the photoresist as shown in FIG. 8.
Compared with the region B inside the n-type well NW1, a doped amount of n-type impurities may be dispersed in the regions A1 and A2 (lying in the periphery of the n-type well NW1), which thus have uneven impurity density. That is, the present inventors regard the dispersion of impurity density in the n-type well NW1 as the significant factor causing variations of threshold voltages Vth of the PMOS transistors 2-P1a and 2-P1b. 
Due to the disposition of the dummy sense amplifier circuits at both ends of the alignment of numerous sense amplifier circuits, the reflection of n-type impurities and the unwanted formation of ion-implantation-incomplete regions due to the shade of the photoresist may occur in the left and right sides in the horizontal direction (X-direction in FIG. 7) of the n-type well NW1 in FIG. 7. In other words, the sense amplifier circuit may not suffer from negative influences such as the reflection of n-type impurities in the vertical direction (Y-direction in FIG. 7) in which a relatively large distance can be secured between the boundary of the n-type well NW1 and the sense amplifier circuits due to the arrangement of the dummy sense amplifier circuits.
With respect to the left-side sense amplifier in FIG. 7, the PMOS transistor 2-P1a is arranged in the region A1, which is close to the boundary of the n-type well NW1, in comparison with the PMOS transistor 2-P2a arranged in the region B. Due to the arrangement in the region A1, the PMOS transistor 2-P1a must be affected by the reflection of n-type impurities (used for the formation of the n-type well NW1 by way of ion implantation) at the side wall of the photoresist; hence, it must suffer from relatively large dispersion of the threshold voltage Vth and have difficulty in precisely controlling the threshold voltage Vth unless it is formed in the region B. For this reason, the difference of the threshold voltage Vth between the PMOS transistor 2-P1a (formed in the region A1) and the PMOS transistor 2-P2a (formed in the region B) may become larger than the potential difference ΔV, which makes the sense amplifier fail to read data from the memory cell.
With respect to the right-side sense amplifier, the PMOS transistor 2-P1b is arranged in the region A2, which is close to the boundary of the n-type well NW1, in comparison with the PMOS transistor 2-P2b arranged in the region B. Therefore, the PMOS transistor 2-P1b must suffer from relatively large dispersion of the threshold voltage Vth and have difficulty in precisely controlling the threshold voltage Vth. Similar to the left-side sense amplifier, the right-side sense amplifier fails to read data from the memory cell.
When the density of n-type impurities of the region A1 is higher than the density of n-type impurities of the region B in the n-type well NW1, the threshold voltage Vth of the PMOS transistor 2-P1a arranged in the region A1 must become higher than the threshold voltage Vth of the PMOS transistor 2-P2a arranged in the region B. When the difference of the threshold voltage Vth between the PMOS transistors 2-P1a and 2-P2a becomes higher than the potential difference ΔV, the sense amplifier may fail to read data from the memory cell.
Progressing fine structures and low-voltage driving in semiconductor memories further reduces the potential difference ΔV, whereby differences of threshold voltages of paired NMOS transistors and differences of threshold voltages of paired PMOS transistors significantly affect the performance of sense amplifiers; hence, it is necessary to reduce dispersions of threshold voltages.
The PMOS transistors 2-P1a and 2-P1b can be rearranged from the regions A1 and A2, wherein the PMOS transistors 2-P1a and 2-P1b and the PMOS transistors 2-P2a and 2-P2b are formed in the region B, which is substantially distanced from the boundary of the n-type well NW1. However, the overall layout area of chips must be increased by securing the substantial distance between the region B and the boundary of the n-type well NW1. This pushes up the manufacturing cost for manufacturing semiconductor devices having numerous sense amplifier circuits due to high memory capacities.
The above description is referred to negative influences due to unwanted variations of densities of n-type impurities relative to variations of threshold voltages of PMOS transistors forming sense amplifiers. Similar arguments can be repeated with respect to the formation of NMOS transistors in p-type wells doped with p-type impurities, wherein due to deviations of ion implantation during the formation of p-type wells, the densities of p-type impurities must be varied in peripheries of p-type wells. Therefore, it is preferable to rearrange NMOS transistors used for sense amplifiers whose threshold voltages are precisely controlled in prescribed regions which are substantially distanced from boundaries of p-type wells.
Characteristic parameters causing negative influences due to dispersion of impurity density in a well are not limited to threshold voltages of transistors; that is, it is possible to list other characteristic parameters such as inter-channel leakage current of transistor, junction capacitance of diode having junctions in the well, junction leakage current, and breakdown voltages of junction.